From the birth of the first integrated circuits at 1960, the number of device on a chip has grown in an explosive increasing rate. In recent year, the progress of semiconductor technology has driven the integrated circuits technologies toward Ultra Large Scale Integration (ULSI) level or even higher level. In ULSI, some negative effects result from the higher integration of devices and the smaller scale of devices. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device is the most important and widely applied devices in the integrated circuits technologies.
To satisfy the requirement for high speed circuit operation and high density of ULSI level, the ultra-short channel Metal Oxide Semiconductor (MOS) device was proposed. One of some articles relates to the ultra-short channel MOS device. Please see "Performance and Reliability Optimization of Ultra Short Channel CMOS Device for Giga-bit DRAM Applications, 1995, IEEE, IEDM 95-435". However, it is difficult to define the gate length to be below 0.1 .mu.m due to the limitation of current optical lithography. One of some articles relates to the above problems. Please see "SUB-50 NM GATE LENGTH N-MOSFETS WITH 10 NM PHOSPHORUS SOURCE AND DRAIN JUNCTIONS, 1993, IEEE, IEDM 93-119".
For realizing high speed and low power ULSI devices, the conventional Complementary Metal Oxide Semiconductor (CMOS) device has been designed with thin gate oxide and short channel length. But the technology of fabricating CMOS devices will increase the gate to drain capacitance. Because the parasitic capacitance is consisted of the gate capacitance, the gate to drain capacitance, the junction capacitance and the gate fringing capacitance, the increasing gate to drain capacitance will augment the parasitic capacitance. So, minimizing the gate to drain capacitance is another key issue for realizing high speed and low power ULSI devices. One of some articles relates to the above problems. Please see "Impact of Reduction of the Gate to Drain Capacitance on Low Voltage Operated CMOS Devices, 1995 Symposium on VLSI Technology Digest of Technical Papers". The above article proposes a new Transistor-gate (T-gate) CMOS device with dual gate structure using amorphous-Si/Polysilicon layer in order to reduce the gate to drain capacitance without the transconductance degradation.
The gate fringing field capacitance (CFR) becomes more important as the gate length is reduced to deep sub-.mu.m. One of some articles relates to the above problems. Please see "A Gate-side Air-gap Structure (GAS) to Reduce the Parasitic Capacitance in MOSFETs , 1996 Symposium on VLSI Technology Digest of Technical Papers".
So, solving above problems is required.